Alif Semiconductor /AE302F80C1557LE_CM55_HP_View /OSPI0 /OSPI_RXFTLR

Receive FIFO Threshold. Controls the level of entries (or above) at which the receive FIFO controller triggers an interrupt. The FIFO depth is 256. If the value in this bit field is greater than the depth of the FIFO, this bit field is not written and retains its current value. When the number of receive FIFO entries is greater than or equal to this value + 1, the receive FIFO full interrupt is triggered.